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Aegis › Readiness & Timeline
Readiness & Timeline

How to Read Our Honest Gates

A short guide to interpreting the gate figures: what they are, what they are not, and why we never translate them into cost.

What a gate figure is

Each gate figure is a physics or engineering result from our models: 3–3.9x plug overstress, 166–830x regime distance, ~400x fuel gap, 30–100x availability shortfall against 0.99982. They quantify the distance between the current design and a fielded machine.

Plug overstress3–3.9xRegime distance166–830xFuel gap~400xAvailability shortfall30–100x

What a gate figure is not

Why we lead with them

Most fusion communication hides its gates. Leading with them lets a technical reader judge the design on its real state. A gate that shrinks over time is evidence of progress; a gate that is denied is a warning sign in any project.

The strongest signal a technical reader can look for is direction: a gate that shrinks over successive results is real evidence of progress, while a gate that is denied or quietly dropped is a warning in any project. We keep the figures identical across every page and frozen under change control, because candor is only credible if it is uniform and does not soften from one page to the next.

See the four gates and the scorecard.

Content reviewed August 2026 · design-and-simulation stage