Static Timing Analysis
Static timing analysis verifies that every path in a chip meets its timing without simulating any specific input pattern.
Checking Every Path at Once
A chip works only if every signal arrives when it is needed. Simulating enough input patterns to prove this is hopeless for a large design. Static timing analysis (STA) instead examines the circuit's structure directly, computing worst-case delays along every timing path without needing input vectors. It is exhaustive and fast, which is why it is the standard sign-off method for timing.
Setup and Hold Checks
STA verifies two constraints at each flip-flop. A setup check ensures data arrives early enough before the clock edge; violating it means the path is too slow for the target frequency. A hold check ensures data does not arrive too early and overwrite the value being captured; violating it means a path is too fast relative to the clock. Setup failures can be cured by slowing the clock, but hold failures cannot, which makes them especially serious.
- Setup: data must be stable before the edge, worst-case slow path
- Hold: data must remain stable after the edge, worst-case fast path
- Slack = required time minus arrival time; negative slack is a violation
Slack and Critical Paths
For each path STA computes slack: how much timing margin it has. Positive slack means the path meets timing; negative slack means it fails. The path with the least slack is the critical path, and it sets the maximum clock frequency. Optimizing a design for speed is largely about finding and shortening critical paths.
Corners and Sign-off
Delays vary with process, voltage, and temperature, so STA is run across multiple corners (worst-case and best-case combinations) to guarantee the chip works everywhere in its operating range. On-chip variation and clock uncertainty are added as margins. When every path meets timing across every required corner, the design has achieved timing closure, a milestone that gates fabrication.