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Digital Logic & Circuits

JK Flip-Flop

A JK flip-flop extends the SR flip-flop by defining the once-forbidden input combination as a toggle.

What it does

A JK flip-flop has two inputs, J and K, that behave like set and reset. J alone sets the output to 1, K alone resets it to 0, and both low holds the value. The key addition is that when both J and K are high the output toggles, flipping on each clock edge.

Behavior table

JKQ next
00Q (hold)
010
101
11NOT Q (toggle)

Why the toggle helps

The SR flip-flop leaves the both-inputs-high case undefined. By defining it as a toggle instead, the JK flip-flop removes any forbidden state and gains a useful mode. Tying J and K together turns it into a T flip-flop.

Edge triggering

JK flip-flops must be edge-triggered. A level-sensitive JK with both inputs high would toggle repeatedly while the clock is high, an unstable condition called racing. Edge triggering limits it to one toggle per clock edge.

Uses

The toggle mode makes JK flip-flops convenient for counters and frequency dividers, though modern designs often use D flip-flops with logic in front, since D flip-flops map more directly to standard cells.