Clock Domains and Metastability
A flip-flop clocked while its input is changing can enter metastability, hovering between 0 and 1 for an unbounded time.
Setup and Hold
A flip-flop reliably captures its input only if that input is stable for a setup time before the clock edge and a hold time after it. Within a single clock domain, timing analysis guarantees these windows are respected. The problem arises when a signal changes right at the edge, which is unavoidable when a signal crosses from one clock domain to another.
What Metastability Is
If the setup or hold requirement is violated, the flip-flop can enter a metastable state: its output sits at an invalid intermediate voltage, neither a clean 0 nor a clean 1, for an unpredictable time before resolving to one or the other. During this interval, downstream logic that samples the output may read inconsistent values, causing failures that are rare, random, and maddening to debug.
- Cause: data edge lands inside the setup/hold window
- Effect: output lingers at an undefined level
- Resolution: eventually settles, but the settling time is unbounded
Mean Time Between Failures
Metastability cannot be eliminated, only made astronomically unlikely. The probability that a flip-flop is still metastable after a given time falls exponentially with that time. Designers quantify this as a mean time between failures that depends on the clock and data rates and on the technology's resolution time constant. The goal is to make the expected failure interval longer than the life of the product.
Why It Is Fundamental
No circuit can decide instantly which side of a threshold an input is on when the input is arbitrarily close to that threshold; this is a physical limit, not a design flaw. It is a hardware echo of undecidability: a bounded-time arbiter that always gives a clean answer is impossible. The practical response is synchronization, the subject of clock-domain crossing, which trades a small, controlled latency for an exponentially improved reliability.