Scan Chains and Design for Test
Scan chains stitch a chip's flip-flops into shift registers so manufacturing defects can be detected after fabrication.
Testing What You Cannot Probe
A fabricated chip may contain manufacturing defects: a shorted wire, an open connection, a stuck transistor. With millions of internal flip-flops that no external pin can directly reach, proving a chip is defect-free is hard. Design for test (DFT) adds structures that make internal state controllable and observable, and the central technique is the scan chain.
How Scan Works
Each ordinary flip-flop is replaced by a scan flip-flop with a multiplexer on its input: in normal mode it works as usual, but in scan mode it takes its input from the previous flop in a chain. All the scan flops are stitched into one or more long shift registers. A tester can then shift an arbitrary pattern into every flip-flop, run one clock cycle of normal operation, and shift the captured results out to compare against expected values.
- Shift in: load a known test pattern into all flops
- Capture: one functional clock applies the pattern through the logic
- Shift out: read the results and compare to the expected response
Fault Models and Coverage
Test patterns are generated against fault models, idealized defects like a node stuck at 0 or stuck at 1, or a bridging short. Automatic test pattern generation computes patterns that expose as many modeled faults as possible, measured as fault coverage. High coverage means most defective chips will fail the test and be caught before shipping.
Built-In Self-Test and Boundary Scan
Built-in self-test puts pattern generation and result checking on the chip itself, useful for memories and for field testing. Boundary scan (the JTAG standard) extends the idea to the pins, letting testers check the connections between chips on a board without physical probes. Together these make complex systems testable at manufacture and in the field, which is essential for the reliable electronics that instrument and control demanding experimental hardware.