Carry-Save Adder

A carry-save adder sums three numbers into two without propagating carries, deferring the single slow carry step until the very end.

The Idea

An ordinary ripple-carry adder chains a carry from bit to bit, so its delay grows with word width. A carry-save adder (CSA) sidesteps this. It takes three input vectors and produces two output vectors: a partial-sum vector and a carry vector. Crucially, no carry travels sideways during this step, so the delay is a single full-adder regardless of word width.

Each bit position holds an independent full adder. Given inputs a, b and c at position i, the full adder emits sum s_i = a_i XOR b_i XOR c_i and carry k_i = majority(a_i, b_i, c_i). The carry vector is shifted left by one before being fed forward, because a carry has twice the weight of the sum bit that produced it.

Why It Matters

CSAs are the workhorse of fast arithmetic. When many numbers must be added, as in a multiplier's partial-product reduction, a tree of carry-save adders collapses n operands to two in logarithmic depth. Only that final pair is combined by one carry-propagating adder, so the expensive carry chain is paid once instead of at every stage.

Three-to-Two Compression

A single CSA is a 3:2 compressor: three inputs, two outputs of the same weight profile. Chaining CSAs lets a design reduce a large stack of partial products quickly. This principle underlies the Wallace and Dadda multiplier trees, where the reduction depth, not the operand count, sets the latency.

Because each column operates independently, a carry-save array is easy to pipeline and lays out regularly in silicon. The trade is that the intermediate result is redundant: two vectors represent one number, and you must resolve them with a final adder before the value is usable elsewhere.