D Latch
A D latch stores the value on its data input while enabled and holds the last value when disabled, with no forbidden state.
What it does
A D latch, or transparent latch, has a data input D and an enable input E. While E is high the latch is transparent: the output follows D. When E goes low the latch holds whatever value D had at that moment. It stores one bit cleanly.
From the SR latch
The D latch is derived from a gated SR latch by connecting D to the set input and NOT D to the reset input. Because S and R are always opposite, the forbidden state can never occur, removing the SR latch's main flaw.
Level-sensitive
The D latch is level-sensitive: it responds to the enable level, not an edge. During the whole time enable is high, changes on D pass straight through. This transparency is useful but can cause problems in synchronous systems, where an edge-triggered element is preferred.
Behavior table
| E | D | Q next |
|---|---|---|
| 0 | 0 | Q (hold) |
| 0 | 1 | Q (hold) |
| 1 | 0 | 0 |
| 1 | 1 | 1 |
Latch versus flip-flop
Because it is transparent, a D latch cannot safely capture and hold on a single clock edge. Cascading two D latches driven by opposite clock phases yields an edge-triggered D flip-flop, the standard storage element in clocked designs.