Clock Divider

A clock divider produces a slower clock from a faster one by counting edges, supplying different parts of a system with different rates.

What it does

A clock divider takes an input clock and outputs a clock at a lower frequency, an integer fraction of the original. Systems need it because different blocks run best at different rates, yet all should derive from one reference for predictable timing.

Divide by two

A single T flip-flop in toggle mode divides frequency by exactly two: it flips once per input edge, so its output completes one cycle for every two input cycles. Its output has an exact 50 percent duty cycle.

Divide by powers of two

Chaining n toggle flip-flops, each clocked by the previous stage's output, divides by 2^n. This is the same structure as a ripple counter, where each bit is a successively slower clock. The higher bits are lower-frequency clocks.

Arbitrary division

To divide by a value that is not a power of two, a synchronous counter counts input edges up to N and resets, producing one output pulse per N input cycles. Achieving a 50 percent duty cycle for odd divisors takes extra logic, such as toggling on both edges.

Uses

Clock dividers generate the multiple clock rates in a system, produce baud rates for serial links, and create the slow ticks used for timing and display refresh.