Clock-Domain Crossing
Clock-domain crossing techniques move signals safely between circuits on unrelated clocks despite the risk of metastability.
When Clocks Do Not Agree
A large chip has many clock domains running at different frequencies or phases: a processor, a memory interface, several peripherals. A signal generated in one domain and sampled in another can land inside the receiver's setup or hold window, risking metastability. Clock-domain crossing (CDC) is the discipline of transferring signals across this boundary reliably.
Synchronizing a Single Bit
The standard tool for a single-bit control signal is a two-flop synchronizer: two flip-flops in series clocked by the receiving domain. If the first flop goes metastable, the second gives it a full clock period to settle before its value is used, making the odds of a metastable value escaping vanishingly small. Adding a third flop lengthens the resolution time further for very high reliability.
- Two-flop synchronizer: for single-bit level or pulse signals
- Never synchronize a multi-bit bus flop-by-flop; bits may resolve on different cycles
- Use handshakes or FIFOs for multi-bit data
Multi-Bit Data
Synchronizing each bit of a bus independently is unsafe: different bits may settle on different cycles, producing a value that never actually existed. The correct approaches are a handshake, where a synchronized request/acknowledge pair guarantees the bus is stable before it is read, and an asynchronous FIFO, which buffers data between domains and uses Gray-coded pointers, changing only one bit at a time, to cross the clock boundary safely.
Gray Codes and Verification
A Gray code is used for FIFO pointers because consecutive values differ by exactly one bit, so even if the pointer is sampled mid-change the receiver reads either the old or new value, never a corrupted intermediate. CDC bugs escape ordinary timing analysis, so dedicated CDC verification tools check that every crossing is properly synchronized, a routine and essential step in modern chip sign-off.