Logic Synthesis
Logic synthesis transforms a register-transfer HDL description into an optimized network of real gates from a technology library.
From Behavior to Gates
Engineers write hardware at the register-transfer level (RTL): registers and the combinational logic that computes their next values. Logic synthesis is the automated step that turns this abstract description into a concrete gate-level netlist, a list of specific logic cells and the wires between them, chosen from a technology library and optimized to meet constraints.
The Stages
Synthesis proceeds in phases. First it elaborates the RTL into generic Boolean logic and inferred registers. Then it performs technology-independent optimization, simplifying Boolean expressions and sharing common sub-logic. Finally it does technology mapping, matching the optimized logic to the actual cells (specific gate and flip-flop types) available in the target library.
- Elaboration: RTL to generic logic and registers
- Optimization: Boolean simplification and resource sharing
- Mapping: choose real library cells for each function
Constraints Drive Everything
Synthesis is guided by constraints: the target clock period, input and output timing, drive strengths, and area or power limits. The tool trades among timing, area, and power to satisfy them. Asking for a faster clock makes the tool pick larger, faster cells and duplicate logic to shorten paths; relaxing timing lets it shrink area and power. These constraints are the primary way a designer steers the result.
Verification and Output
Because synthesis rewrites the logic, the result must be checked to still match the RTL. Formal equivalence checking proves the gate-level netlist is logically identical to the source, catching any tool error. The synthesized netlist, annotated with timing constraints, is then handed to place and route to be given a physical location on the chip. Modern flows fold in preliminary timing estimates so synthesis does not produce a netlist that later proves impossible to route or time.