Phase-Locked Loop
A phase-locked loop generates a clock locked in phase and frequency to a reference, and can multiply frequency for on-chip clocking.
Locking to a Reference
A phase-locked loop (PLL) is a feedback circuit that produces an output clock whose phase and frequency track an input reference. It compares the phases of the reference and its own output, and adjusts an internal oscillator until they align. Once locked, the output stays synchronized to the reference even as conditions drift.
The Feedback Loop
A PLL has three core parts. A phase detector measures the phase difference between the reference and the feedback signal. A loop filter smooths that error into a slowly varying control voltage. A voltage-controlled oscillator produces the output clock at a frequency set by that voltage. The output is fed back to the phase detector, closing the loop so the error is continually driven toward zero.
- Phase detector: compares reference and feedback phase
- Loop filter: turns phase error into a stable control signal
- Voltage-controlled oscillator: generates the output frequency
Frequency Multiplication
Placing a frequency divider in the feedback path is what makes PLLs indispensable on chips. If the feedback divides the output by N before comparison, the loop forces the output to run at N times the reference frequency. This lets a chip take a modest crystal reference and synthesize the high-frequency clocks its logic needs, and lets different blocks run at different multiples of one reference.
Jitter, Lock, and Use
Real PLLs must balance fast locking against low jitter (cycle-to-cycle timing noise) and stability, tuned through the loop filter's bandwidth. They also recover clocks from serial data streams and de-skew clock distribution. Nearly every complex digital chip contains several PLLs to generate and manage its clock domains, making them foundational to timing across the whole system.