D Flip-Flop

A D flip-flop captures its data input on a clock edge and holds it until the next edge, the standard storage element of synchronous logic.

What it does

A D flip-flop samples the value on its data input D at the moment of a clock edge, usually the rising edge, and holds that value on its output Q until the next edge. Between edges, changes on D are ignored. This edge-triggered behavior is what makes synchronous design predictable.

Master-slave construction

A common D flip-flop is two D latches in series driven by opposite clock phases. While the clock is low the master latch is transparent and tracks D; on the rising edge the master freezes and the slave becomes transparent, passing the captured value to the output. Only the value at the edge survives.

Timing requirements

D must be stable for a setup time before the edge and a hold time after it. Violating these windows can drive the flip-flop into a metastable state where the output is briefly undefined. See setup and hold time.

Control inputs

Practical flip-flops add asynchronous set and reset inputs to force a known state at power-up, and often a clock-enable input that lets the flip-flop ignore edges while holding its value.

Uses

D flip-flops build registers, pipeline stages, and the state memory of finite state machines. They are the most widely used sequential element in digital systems.