Cache Coherence and MESI
When multiple cores cache the same memory, a coherence protocol like MESI keeps their private copies consistent.
The Coherence Problem
In a multiprocessor, each core has its own private cache. If two cores both cache the same memory block and one writes it, the other's copy becomes stale. A cache coherence protocol ensures that all cores see a single, consistent value, as if there were one shared memory, without forcing every access back to slow main memory.
The Four States
MESI gives each cached line one of four states:
- Modified: this cache holds the only copy and it is dirty (memory is stale)
- Exclusive: this cache holds the only copy and it is clean (matches memory)
- Shared: the line is clean and may exist in other caches too
- Invalid: the line holds no valid data
The Exclusive state is the clever part: it lets a core that is the sole holder of a clean line silently upgrade to Modified on a write, with no bus traffic, because it knows no one else has a copy.
Snooping and Transitions
Cores watch (snoop) a shared bus or interconnect for other cores' memory transactions. When a core wants to write a Shared line, it issues an invalidate so every other copy transitions to Invalid; the writer moves to Modified. When a core reads a line another holds Modified, that owner supplies the current data and both settle into Shared, with memory updated.
| state | readable | writable | unique |
|---|---|---|---|
| M | yes | yes | yes |
| E | yes | yes | yes |
| S | yes | no | no |
| I | no | no | no |
Beyond MESI
Extensions add states for efficiency. MOESI adds an Owned state so a dirty line can be shared without writing back to memory first; MESIF adds a Forward state so one designated sharer answers read requests. Large systems replace bus snooping with directory-based coherence, which tracks which cores hold each block and sends point-to-point messages, scaling to many more cores than a shared bus can.