Quench Detection Hardware

Above the passive failsafe, an FPGA estimator fuses co-wound voltage, thermometry, and REBCO strain to detect quenches earlier and localize them.

Two tiers of protection

The passive failsafe is the floor. Above it, L1 runs an FPGA-based quench detector that is faster and smarter than a single comparator: it fuses multiple signals to reject false trips and to localize the event, so response can be selective rather than dumping the entire magnet on every anomaly.

Signal fusion

The estimator combines co-wound voltage taps (resistive voltage), distributed thermometry (ΔT and its rate), and REBCO strain gauges (mechanical disturbance that can precede a conductor motion event). A bridge subtraction cancels the inductive component of tap voltage, V_res = V_tap − M dI/dt, isolating the resistive term that signals a normal zone. This runs in fabric every clock, so detection latency is a fixed pipeline depth.

False-trip rejection

Spurious dumps are costly to availability, so the detector requires coincidence: a resistive-voltage rise and a temperature-rate rise in the same conductor region within a short window. Inductive pickup from a fast current ramp lacks the thermal signature; a coolant transient lacks the resistive signature. Only a true normal zone shows both.

• V_res isolation via inductive-term cancellation.
• Temperature-rate coincidence gate.
• REBCO strain as an early mechanical cue.
• Spatial localization from segmented taps to target the response.

Handoff to action

When the FPGA detector confirms a quench it commands the bypass dump and coordinated slow dump, and raises the machine's protective interlocks. Critically, it can only act faster than the passive floor, never slower: if the FPGA path is unavailable, the analog comparator chain still fires. Both machines share this hardware, tuned to the breeder's 16.84 T and the burner's 26.49 T operating points.