Control-Loop Timing Math

Loop period is not chosen by convenience; it is derived from the closed-loop bandwidth required to stabilize the fastest mode the loop must control.

From physics bandwidth to loop period

Each control loop must sample fast enough to observe and act on the dominant mode it stabilizes. A common engineering rule places the sampling rate at 20–40× the closed-loop bandwidth so that the discrete controller behaves like its continuous design and the added phase lag stays small.

import math
def loop_period(f_bw_hz, oversample=30):
    # sample well above the closed-loop bandwidth to bound phase lag
    fs = oversample * f_bw_hz
    return 1.0 / fs                      # loop period, seconds

def phase_lag_deg(T_loop, f_bw_hz):
    # half-sample computational delay -> phase lag at bandwidth
    return 360.0 * f_bw_hz * (T_loop/2.0)

T = loop_period(2_000)                   # 2 kHz mode -> ~17 us period
print(round(phase_lag_deg(T, 2_000),1)) # ~6 deg lag at bandwidth

Vertical stability sets the pace

On the breeder, the vertical instability of an elongated, negative-triangularity (δ = −0.30) plasma is the fastest mode the position loop must catch. Its growth rate sets the required loop bandwidth, which sets the period, which the timing budget must then honor with margin.

def stabilizable(growth_rate_s, loop_bw_hz, margin=5.0):
    # loop bandwidth must exceed the instability growth rate
    gamma_hz = growth_rate_s / (2*math.pi)
    return loop_bw_hz >= margin * gamma_hz

assert stabilizable(growth_rate_s=800.0, loop_bw_hz=1500.0)

Oversampling far above the closed-loop bandwidth also buys robustness to the model error the loop was designed against: the discrete controller stays close to its continuous prototype, so the phase and gain margins computed on paper survive discretization. Under-sampling to save compute is self-defeating here, because the phase lag it introduces is spent from the same stability budget that model uncertainty and transport delay already draw down. The period is therefore chosen from physics first and hardware second, and a loop that cannot be run fast enough on the available fabric is redesigned or re-partitioned rather than run at an unsafe cadence, because a loop sampled too slowly is not a slower controller but an unstable one.

The same derivation runs for the burner's ambipolar potential and end-plug density loops. Where a mode is faster than any digital loop can chase, control is not attempted — the fault is instead handled by a hardware reflex or a passive stabilizing structure. See stability margins and control headroom and vertical displacement arrest.