L1 — Control Plane

Edge FPGAs enforcing sub-10-microsecond determinism, synchronized actuation gates, and the autonomous hardware failsafe that dumps a quench with zero AI dependency.

The hard real-time layer

L1 Control Plane is where the architecture touches the machine at machine speed. It is built on edge FPGAs that guarantee deterministic, jitter-bounded response under 10 microseconds. L1 is the only layer permitted on the safety-critical command path, and it is designed to protect the plant even if every layer above it fails.

What L1 does

• Deterministic actuation of coils, gas and pellet injection, and heating.
• Synchronized gates that fire multiple actuators in lockstep.
• PLC-driven deterministic vacuum interlocks.
• The autonomous hardware failsafe — an independent quench dump with no AI in the loop.

Why FPGAs

FPGAs are chosen for bounded worst-case timing, not average speed. Protecting a REBCO magnet holding 9.66 MA of breeder plasma current, or a 26.49 T burner plug, requires that the response time never exceeds its budget — not merely that it is usually fast. General-purpose processors and their schedulers cannot make that guarantee; deterministic logic can.

Independent of intelligence

L1's defining property is that its safety function does not depend on L3's AI. The autonomous failsafe is triggered by physical thresholds in hardware. If the twin, the network, or the copilots are unavailable, L1 still dumps a developing quench on its own. Intelligence lives above L1; safety lives in it.

L1's timing contract is the sub-10 microsecond boundary; its last-resort function is the autonomous failsafe.