Skip to content
Technology How it works Breeder — Hyperion Burner — Aegis Burner — MetroVolt AI-Native Architecture Magnets Fuel cycle Safety Roadmap
Solutions AI & Data Centers Defense & Government Grid & Baseload Neutron Detection Quantum
Learn Technical Library
Proof Publications Whitepapers Technical Library Open Science & Reproducibility The Honest Gates
Company About / Mission Leadership Environment Health & Safety Investors Careers Press Contact
3D Model
AI Architecture › L1 · Control Plane
L1 · Control Plane

FPGA vs CPU vs GPU for Control

Each compute fabric has a place in Kronos: GPUs for offline training, CPUs for coordination, FPGAs for the timed control and protection paths.

THE STACK · click to jumpL7Ecosystem & StrategyL6Experience & VisualizationL5Applications & CopilotsL4OrchestrationL3Twin Modeling & AIL2Data FabricL1Control PlaneL0Foundation▲tlmctl▼L1 · CONTROL PLANEHard real-time actuation and the autonomous failsafe.1Edge FPGAµs-determinism2Real-Time Actuationcoils · heating · fuel3Hardware Failsafeautonomous trip4Sync Gatephase-locked timing5Signal I/OADC / DAC6Watchdogliveness & interlocksMACHINE TIEDrives magnets, ice-piston, and gas puff on the sub-10 µs loop.KRONOS FUSION ENERGYAI-NATIVE S.M.A.R.T. GENERATORCONTROL PLANESHEET 03REV. 2026-08L1 · AI-NATIVE STACK
L1 · Control Plane — its place in the stack (left, click any layer) and its internal components (right). Telemetry rises; control descends.

The right tool per tier

Kronos does not favor one silicon; it matches fabric to requirement. GPUs deliver throughput for offline multi-physics and model training at L0. CPUs give flexible, ordered coordination at L2/L3. FPGAs give bounded, jitter-free timing at L1. Only the FPGA can promise a cycle-exact deadline, which is why it owns the fast loops on both machines.

Latency and determinism

A comparison

FabricDeterministicFast loop role
FPGAyesprotection + inner loops
CPUnosupervisory + config
GPUnooffline training only

Throughput vs timing

The GPU wins on floating-point throughput per watt for large batched work — exactly what L0's Monte Carlo neutronics and surrogate training need. But throughput is not timing. A control loop needs the same small computation to complete before a fixed deadline every cycle, which favors spatial fabric over time-shared cores. Kronos therefore trains on GPUs, then compiles the resulting gains and thresholds into FPGA fabric.

CPUs remain essential for what is not on the critical path: loading bitstreams, mediating the MPC handoff, logging to the L2 archive, and running the PLC supervisory logic. The architecture is a division of labor, not a contest.

Content reviewed August 2026 · design-and-simulation stage