Flip-Chip Integration
Flip-chip bonding joins a qubit chip face-to-face with a wiring chip using superconducting bumps, separating fragile qubits from lossy routing layers.
The Face-to-Face Stack
In flip-chip integration two chips are fabricated separately and then bonded with their patterned faces toward each other, connected by an array of small superconducting bumps, commonly indium. One chip carries the qubits; the other, the interposer, carries the control and readout wiring, ground planes, and sometimes filters and airbridges. The bumps provide both electrical connection and a precise mechanical spacer that sets the gap between the chips.
Why Separate the Layers
Keeping qubits on their own chip lets that chip be fabricated with the cleanest possible process, free of the dense, potentially lossy wiring. The wiring, which would otherwise crowd the qubit plane and introduce loss, lives on the interposer at a controlled distance. This physical separation can improve coherence while giving the wiring room to fan out, addressing the routing bottleneck of planar devices.
- Superconducting bumps carry signals and set the inter-chip spacing.
- Qubit chip and wiring chip are optimized and fabricated independently.
- The gap distance is a design parameter that tunes coupling and mode structure.
Engineering Challenges
The bumps and their interfaces must be superconducting and low-loss, or they become a source of decay and two-level systems. Alignment between the two chips must be precise, since qubit-to-wiring coupling depends on their relative position and the gap height. Thermal contraction on cooldown, differential stress, and the reliability of thousands of bonds all matter. Any residual normal metal or oxide at the bond can trap quasiparticles or add loss.
Where It Leads
Flip-chip integration is a proven step used in current multi-qubit processors and a foundation for further vertical integration with through-silicon vias and multi-tier stacks. It is one of the concrete techniques that makes the packaging and 3D-integration strategy practical, and it borrows heavily from mature semiconductor packaging while adapting it to the demands of superconducting, low-loss, cryogenic operation.