L1 Control Plane Architecture Overview
The L1 tier is Kronos's hard real-time layer: edge FPGAs and PLCs that convert model intent into microsecond-deterministic actuation for both machines.
What L1 is
The Control Plane (L1) sits between the offline Foundation tier (L0) and the Twin/AI tier (L3), but it is not a place where learning happens. L1 exists to guarantee bounded latency and bounded jitter on every command path that can move energy or open a fault. It hosts the edge FPGA fabric, the deterministic PLC layer, and the actuator drivers that touch the breeder (Hyperion) and the burner (Aegis / MetroVolt).
Kronos's design principle is a strict separation of concerns: intelligence proposes, hardware disposes. L3's model-predictive control (MPC) agents compute setpoint trajectories on a 50–100 ms predictive shadow; L1 accepts those setpoints as advisory targets and enforces them through control loops whose worst-case timing is provable, not statistical.
The layer boundary
Every command crossing into L1 passes a validation gate: range checks, rate-of-change limits, and cross-consistency against the measured state vector. A setpoint that violates a hardware envelope is clamped or rejected at the FPGA edge before it ever reaches a coil supply or a beam modulator. This is why the failsafe path can be certified independently of any machine-learning component.
Both machines, one discipline
- Breeder (Hyperion): equilibrium, vertical stability, negative-triangularity shape control, disruption avoidance.
- Burner (Aegis / MetroVolt): end-plug density, ambipolar potential, direct-energy-conversion (DEC) grid modulation.
- Shared: quench protection, vacuum interlocks, deterministic clock distribution, watchdog supervision.
The remainder of this category documents each loop, its timing budget, and how determinism is preserved from sensor feedthrough to actuator gate. The organizing constraint throughout is the sub-10µs command boundary.