Steady-State Error and System Type
Steady-state error is the residual tracking error after transients settle, set by the number of integrators in the open loop.
The Error That Remains
After a control loop's transients die out, the output may still differ from the reference by a constant amount. This residual is the steady-state error. Its size depends on the shape of the reference (step, ramp, or parabola) and on the structure of the open-loop transfer function, specifically how many pure integrators it contains.
System type
The system type is the number of poles the open-loop transfer function has at the origin, that is, the number of integrators in the loop. Type 0 has none, type 1 has one, type 2 has two. System type determines which reference signals can be tracked with zero steady-state error and which leave a finite or infinite error.
The type-versus-input table
| Type | Step input | Ramp input |
|---|---|---|
| 0 | finite error | infinite |
| 1 | zero error | finite error |
A type-0 system tracks a step with a finite offset and cannot follow a ramp at all. A type-1 system tracks a step with zero error and a ramp with a finite error. A type-2 system tracks both steps and ramps with zero error and a parabola with finite error. Each added integrator promotes the loop to track one more class of input exactly.
The error constants
- Position constant Kp governs step error; larger Kp means smaller step error, zero when Kp is infinite.
- Velocity constant Kv governs ramp error; a finite Kv gives a constant lag behind a ramp.
- Acceleration constant Ka governs parabolic error.
- Each constant is a low-frequency limit of the loop gain and is raised by increasing gain or adding integrators.
The trade-off
Adding integrators to eliminate steady-state error is powerful but not free: each integrator adds 90 degrees of phase lag, eroding stability margin and making the loop harder to stabilize. This is why most loops use one integrator (type 1) to kill step error while keeping stability manageable, and reserve a second integrator only when ramp-tracking accuracy truly requires it.
This connects to the internal model principle: to track or reject a signal with zero steady-state error, the loop must contain a model of that signal's generator, which for polynomial references means the corresponding number of integrators.