Interrupt Handling and Latency
Interrupts let hardware demand prompt attention; interrupt latency, the delay before the response begins, is a key determinant of real-time responsiveness.
What Interrupts Do
An interrupt is a hardware signal that diverts the processor from its current work to handle an event, such as a completed conversion, an arriving packet, or a timer tick. Interrupts let a system respond to events without polling, which saves the processor from spinning in wait loops and enables fast reaction.
Interrupt Latency
Interrupt latency is the time from the hardware asserting the interrupt to the first instruction of the handler executing. It has several contributors: the time the current instruction takes to reach an interruptible point, any interval during which interrupts are disabled, the time to save context and vector to the handler, and delays from higher-priority interrupts running first. In a real-time system the worst-case latency, not the typical, is what matters.
Keeping Latency Bounded
- Minimize and bound the longest interrupt-disabled interval in all code
- Keep handlers short: do the minimum in the handler, defer the rest
- Assign interrupt priorities so critical sources are not delayed by trivial ones
- Avoid long non-preemptible critical sections in the kernel
Top and Bottom Halves
A common pattern splits interrupt work into two parts. The top half, the handler itself, does only the urgent, minimal work: acknowledge the hardware, capture a timestamp or sample, and signal a task. The bottom half, a scheduled task or deferred routine, does the heavier processing at normal priority. This keeps the time spent with interrupts disabled small, which lowers the worst-case latency seen by every interrupt source.
Interrupts Versus Determinism
Interrupts improve responsiveness but complicate determinism, because an interrupt can preempt a task at an unpredictable moment and adds interference to its timing. For the most timing-critical periodic work, some designs prefer a purely time-triggered approach driven by a single timer interrupt, or move the operation into hardware, trading the flexibility of many interrupts for tighter predictability.